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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Startup Event Register (R08h/R09h)
The Startup Event register (R08h/R09h, Table 11) records
port startup failure events and current-limit disconnect
timeout events. On power-up or after a reset condition, the
Fault Event register is set to a default value of 00h. ICV_ is
set to 1 when a port shuts down due to an extended cur-
rent-limit event after startup. TSTART is set to 1 whenever
a port fails startup due to an overcurrent or current-limit
event during startup. As with the other event registers,
the Startup Event register has two addresses. When read
through the R08h address, the content of the register
is left unchanged. When read through the CoR R09h
address, the register content is reset to the default state.
Supply Event Register (R0Ah/R0Bh)
The device monitors die temperature, external FET sta-
tus, and the analog and digital power supplies, and sets
the appropriate bits in the Supply Event register (R0Ah/
R0Bh, Table 12). On power-up or after a reset condition,
Table 11. Startup Event Register
the Supply Event register is set to a default value of 02h
(but may immediately change depending on the cause
of the reset).
A thermal-shutdown circuit monitors the temperature of
the die and resets the device if the temperature exceeds
+140 N C. TSD is set to 1 after the device recovers from
thermal shutdown and returns to normal operation.
If a FET failure is detected on one or more ports, FETBAD
is set high. To determine which port the failure was
detected on, check the FET_BAD_ bit in the HP Status
register of each port (Table 42). FET_BAD_ is set to 1 if
the port is powered, there is no current-limit condition,
and V OUT_ - V EE > 2V.
When V EE or V DD are below their UVLO thresholds, the
device is in reset mode and securely holds the port off.
When they rise above the UVLO threshold, the device
comes out of reset and the appropriate V DD_UVLO /
V EE_UVLO bit in the Supply Event register is set to 1.
ADDRESS =
SYMBOL BIT NO.
08h
TYPE
09h
TYPE
DESCRIPTION
ICV4
ICV3
ICV2
ICV1
TSTART4
TSTART3
TSTART2
TSTART1
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
Current-limit disconnect timeout on port 4
Current-limit disconnect timeout on port 3
Current-limit disconnect timeout on port 2
Current-limit disconnect timeout on port 1
Startup failure on port 4
Startup failure on port 3
Startup failure on port 2
Startup failure on port 1
Table 12. Supply Event Register
ADDRESS =
SYMBOL BIT NO.
0Ah
TYPE
0Bh
TYPE
DESCRIPTION
TSD
FETBAD
V DD_UVLO
V EE_UVLO
Reserved
Reserved
Reserved
Reserved
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
Overtemperature shutdown
FETBAD is set if a FET failure is detected on one or more ports
V DD undervoltage-lockout condition
V EE undervoltage-lockout condition
Reserved
Reserved
Reserved
Reserved
33
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